Vertically stacked-NanoWires MOSFETs in a replacement metal gate process with inner spacer and SiGe source/drain

2016 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2016-12-01 DOI:10.1109/IEDM.2016.7838441

S. Barraud, V. Lapras, M. Samson, L. Gaben, L. Grenouillet, V. Maffini-Alvaro, Y. Morand, J. Daranlot, N. Rambal, B. Previtalli, S. Reboh, C. Tabone, R. Coquand, E. Augendre, O. Rozeau, J. Hartmann, C. Vizioz, C. Arvet, P. Pimenta-Barros, N. Possémé, V. Loup, C. Comboroure, C. Euvrard, V. Balan, I. Tinti, G. Audoit, N. Bernier, D. Cooper, Z. Saghi, F. Allain, A. Toffoli, O. Faynot, M. Vinet

{"title":"Vertically stacked-NanoWires MOSFETs in a replacement metal gate process with inner spacer and SiGe source/drain","authors":"S. Barraud, V. Lapras, M. Samson, L. Gaben, L. Grenouillet, V. Maffini-Alvaro, Y. Morand, J. Daranlot, N. Rambal, B. Previtalli, S. Reboh, C. Tabone, R. Coquand, E. Augendre, O. Rozeau, J. Hartmann, C. Vizioz, C. Arvet, P. Pimenta-Barros, N. Possémé, V. Loup, C. Comboroure, C. Euvrard, V. Balan, I. Tinti, G. Audoit, N. Bernier, D. Cooper, Z. Saghi, F. Allain, A. Toffoli, O. Faynot, M. Vinet","doi":"10.1109/IEDM.2016.7838441","DOIUrl":null,"url":null,"abstract":"We report on vertically stacked horizontal Si NanoWires (NW) /»-MOSFETs fabricated with a replacement metal gate (RMG) process. For the first time, stacked-NWs transistors are integrated with inner spacers and SiGe source-drain (S/D) stressors. Recessed and epitaxially re-grown SiGe(B) S/D junctions are shown to be efficient to inject strain into Si/-channels. The Precession Electron Diffraction (PED) technique, with a nm-scale precision, is used to quantify the deformation and provide useful information about strain fields at different stages of the fabrication process. Finally, a significant compressive strain and excellent short-channel characteristics are demonstrated in stacked-NWs /-FETs.","PeriodicalId":186544,"journal":{"name":"2016 IEEE International Electron Devices Meeting (IEDM)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"69","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE International Electron Devices Meeting (IEDM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2016.7838441","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 69

Abstract

We report on vertically stacked horizontal Si NanoWires (NW) /»-MOSFETs fabricated with a replacement metal gate (RMG) process. For the first time, stacked-NWs transistors are integrated with inner spacers and SiGe source-drain (S/D) stressors. Recessed and epitaxially re-grown SiGe(B) S/D junctions are shown to be efficient to inject strain into Si/-channels. The Precession Electron Diffraction (PED) technique, with a nm-scale precision, is used to quantify the deformation and provide useful information about strain fields at different stages of the fabrication process. Finally, a significant compressive strain and excellent short-channel characteristics are demonstrated in stacked-NWs /-FETs.

查看原文本刊更多论文

垂直堆叠的纳米线mosfet在替代金属栅极工艺与内部间隔和SiGe源/漏

我们报道了用替代金属栅极(RMG)工艺制造的垂直堆叠水平硅纳米线(NW) / - mosfet。第一次，堆叠nws晶体管集成了内部间隔器和SiGe源漏(S/D)应力源。凹形和外延再生SiGe(B) S/D结被证明可以有效地向Si/-通道注入应变。采用纳米级精度的进动电子衍射(PED)技术，对材料的变形进行了量化，并提供了不同加工阶段应变场的有用信息。最后，在堆叠- nws /- fet中证明了显著的压缩应变和优异的短通道特性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

求助全文

约1分钟内获得全文求助全文

来源期刊

2016 IEEE International Electron Devices Meeting (IEDM)

自引率

0.00%

发文量