Multi-Phase Fault Detection and Analysis in FPGA Interconnects

Abstract

With the increase in integration density in FPGA devices, the possibility of interconnect faults are increasing. Various fault diagnosis approach were observed for the detection of faults in FPGA, through the conventional ATE. These devices are designed for the detection of logical faults occurring in the operation of the FPGA. The ATE devices are currently designed to diagnosis the FPGA operation for faults and intern the fault detection is rectified by reprogramming the device. The localization of such faults will result in faster fault diagnosis. In this paper an approach for faults in FPGA interconnects is developed called forward tree coding. The approach is developed to isolate the fault region in a defined FPGA to reduce the time to market of digital devices. The designing and realization of the suggested approach on a targeted Xilinx device is also developed to evaluate its real time feasibility.