A 35-39 GHz CMOS Linearized Receiver with 2 dBm IIP3 and 16.8 dBm OIP3 for the 5G Systems

Abstract

A35-39 GHz linearized differential in-phase and quadrature components (I/Q) receiver (Rx) fabricated in 65-nm CMOS for 5G massive front-ends phased-array systems is introduced. The two linearization techniques, multi-gate transistor (MGTR) and splitting cascode transistors (SCTR) linearizers, are adopted at RF amplifier and down-conversion mixers respectively which greatly cancel the 3rd-order intermodulation (IM3) power with P1dB, IP3, and 3rd-harmonic rejection ratio (RR3) enhancements. According to measurements at RF 38 GHz in normal/linearized modes, the IP1dB/OP1dB showed 6 dB/2.4 dB enhancement (IP1dB improved from -19 to -13 dBm, and OP1dB improved from -1.6 to 0.8 dBm.) with 3.6 dB conversion gain (CG) degeneration (18. 4 dB decreased to 14.8 dB). The power consumption is 62.5 mW. According to two-tone measurements, the IM3 power decreased 20-28dB with IIP3lOIP3 enhancement of 13 dB/9.4 dB (IIP3 improved from -11 to 2 dBm, and OIP3 improved from 7.4 to 16.8 dBm The maximum IF power with RR3 value < -40 dBc improved 7 dB (-12 dBm improved to -5 dBm). Furthermore, the quadrature amplitude modulation (QAM) carrier demodulation test is demonstrated. In larger RF/IF power region, the measurement exhibits that the 256 QAM constellation diagram in normal mode is dispersed but recovered in linearized mode due to the improved RR3. Compared with republications, the proposed Rx has good IP1dB, OIP3 values, significant IP1dB, IP3, RR3 improvement with IM3 suppression. This linearized Rx is satisfactory for 5G massive front-ends phased-array systems.