Programmable delay lines on different LUT implementations for CRO-PUF

Abstract

In this paper we analyze the performance of configurable physically unclonable functions based on ring oscillators (CRO-PUFs) implemented in FPGA due to differences in detailed routing at LUT level. The different PUF configurations for a given set of ring oscillators are generated using programmable delay lines on the cells realizing the inverters, while only one LUT input is used for the propagation of the oscillations along the ring. This architecture is suitable for implementation in FPGA, so the experiments have been conducted on Xilinx’s Zynq SoC.