1-Bit Full Adder Output Analysis Using Adiabatic ECRL Technique

Abstract

Design and analysis of an adiabatic adder using Efficient Charge Recovery Logic is discussed. The study also presents the comparison of adiabatic adder with the CMOS logic-based adder. The power clock implementation for the adiabatic adder along with its characteristics have been studied. The performance of the new adiabatic adder counterparts is compared against the CMOS logic-based adders. The adders were simulated using Cadence Virtuoso 6.1.7 spectre simulator tool using 180 nm cmos technology for measurement of power dissipation, delay and PDP at 1.8V supply voltage and 200 MHz frequency. The adders were simulated at voltages ranging from 0.8V to 2.5V for power comparison. Simulation results dictate adiabatic adders can outperform the CMOS based adders in terms of power dissipation almost 45% less and requires lesser number of transistors.