{"title":"A monolithic stacked Class-D approach for high voltage DC-AC conversion in standard CMOS","authors":"P. Callemeyn, M. Steyaert","doi":"10.1109/ESSCIRC.2013.6649098","DOIUrl":null,"url":null,"abstract":"A fully-integrated Class-D DC-AC converter is realized in a 130 nm 1.2V CMOS technology with an on-chip inductor and capacitor. Several dies are combined to achieve higher output power. A multilevel topology allows the combined Class-D DC-AC system to achieve higher output voltages at a multiple of the nominal supply voltage of 1.2V. Problems such as hot carrier degradation and oxide breakdown are absent, since each subblock operates within the standard voltage limits. An off-chip low frequency signal can be used as a reference clock for the Class-D DC-AC converter using an on-chip PWM generation circuit. For this monolithic multilevel system, no discrete components are needed anymore, reducing the bill of materials. A maximum efficiency of 66.5% for a stand-alone die is reached. An output peak voltage of 2.4V peak-to-peak is achieved at an efficiency of 33% by using a combination of several dies. A total output power of 95mW is obtained.","PeriodicalId":183620,"journal":{"name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 Proceedings of the ESSCIRC (ESSCIRC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2013.6649098","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A fully-integrated Class-D DC-AC converter is realized in a 130 nm 1.2V CMOS technology with an on-chip inductor and capacitor. Several dies are combined to achieve higher output power. A multilevel topology allows the combined Class-D DC-AC system to achieve higher output voltages at a multiple of the nominal supply voltage of 1.2V. Problems such as hot carrier degradation and oxide breakdown are absent, since each subblock operates within the standard voltage limits. An off-chip low frequency signal can be used as a reference clock for the Class-D DC-AC converter using an on-chip PWM generation circuit. For this monolithic multilevel system, no discrete components are needed anymore, reducing the bill of materials. A maximum efficiency of 66.5% for a stand-alone die is reached. An output peak voltage of 2.4V peak-to-peak is achieved at an efficiency of 33% by using a combination of several dies. A total output power of 95mW is obtained.