{"title":"Robust 60 GHz 90nm and 40nm CMOS wideband neutralized amplifiers with 23dB gain 4.6dB NF and 24% PAE","authors":"E. Cohen, O. Degani, S. Ravid, D. Ritter","doi":"10.1109/SIRF.2012.6160151","DOIUrl":null,"url":null,"abstract":"A three stage transformer differential cross coupled (CC) LNA and PA with integrated baluns for operation in the 57-66GHz band are presented. The LNA fabricated in a 90nm CMOS process achieves 23dB gain and 4.6dB NF at 13mA and 1.3V supply, with 0.06mm2 in size. The PA, also fabricated in a 90nm CMOS process, has maximum power added efficiency (PAE) of 19.4%, 9.4dBm Psat, and 23dB gain with a 12GHz BW and 0.05mm2 chip size. A 2 stage PA fabricated in a digital 40nm CMOS achieves 19dB gain and a record PAE of 24%. The paper analyzes the advantages of MOScap neutralization feedback compared to metal capacitors and low k transformers for process stability and broadband design. Tuning is added to the CC feedback to compensate for process variations.","PeriodicalId":339730,"journal":{"name":"2012 IEEE 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","volume":"20 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"18","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 IEEE 12th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SIRF.2012.6160151","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 18
Abstract
A three stage transformer differential cross coupled (CC) LNA and PA with integrated baluns for operation in the 57-66GHz band are presented. The LNA fabricated in a 90nm CMOS process achieves 23dB gain and 4.6dB NF at 13mA and 1.3V supply, with 0.06mm2 in size. The PA, also fabricated in a 90nm CMOS process, has maximum power added efficiency (PAE) of 19.4%, 9.4dBm Psat, and 23dB gain with a 12GHz BW and 0.05mm2 chip size. A 2 stage PA fabricated in a digital 40nm CMOS achieves 19dB gain and a record PAE of 24%. The paper analyzes the advantages of MOScap neutralization feedback compared to metal capacitors and low k transformers for process stability and broadband design. Tuning is added to the CC feedback to compensate for process variations.