Dedicated hardware architecture for cycle crossover operation

Abstract

This paper discusses new dedicated hardware architecture for crossover operation in order to achieve high speed processing. The proposed architecture is based on cycle crossover algorithm which has superior search performance. It achieves not only high speed processing, but also reduction of the number of processing steps to obtain a solution. In order to evaluate the proposed architecture, we design the proposed architecture by using Verilog-HDL, and conduct logic simulation and logic synthesis. Simulation results prove the effectiveness of the proposed architecture in comparison with conventional software processing.