FPGA based hardware in the loop test of railway traction system

Chen Liu, Rui Ma, B. Hao, Huan Luo, F. Gao, Franck Gechter
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引用次数: 3

Abstract

Hardware in the loop (HIL) test provides a timesaving and safe environment for testing prototypes. However, the main difficulty for the real time simulation of power electronic system is the modeling method for the complex system. This paper proposes a modeling method for traction system in high speed train for transportation application. In this paper, it proposes hardware in the loop test setup for railway high-speed train with field-programmable gate array (FPGA) boards of dSPACE simulator. Besides, in order to meet the computing power requirement of the system modeling, a multi-processor system of dSPACE is achieved through Gigalink connection. The whole HIL system can be used to evaluate both the hardware and software performance of traction control unit (TCU). The real time simulation results under steady-state and transient conditions demonstrate modeling accuracy and provide detailed insight into the development of this vehicle.
基于FPGA的铁路牵引系统硬件在环测试
硬件在环(HIL)测试为测试原型提供了一个节省时间和安全的环境。然而,电力电子系统实时仿真的主要难点是复杂系统的建模方法。提出了一种适用于交通运输的高速列车牵引系统的建模方法。本文利用dSPACE模拟器的现场可编程门阵列(FPGA)板设计了铁路高速列车的硬件环内测试装置。此外,为了满足系统建模对计算能力的要求,通过Gigalink连接实现了dSPACE的多处理器系统。整个HIL系统可以用来评估牵引控制单元(TCU)的硬件和软件性能。在稳态和瞬态条件下的实时仿真结果验证了建模的准确性,并为该车辆的开发提供了详细的见解。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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