{"title":"A linear selection diode steered core memory","authors":"R. Shevlin","doi":"10.1145/612201.612256","DOIUrl":null,"url":null,"abstract":"In a linearly selected core configuration, the role of selection is removed from the memory core and an external system must be devised to select a desired line of cores. Several systems have been developed using a core switch array to drive the memory. This paper will describe a selection scheme utilizing diodes to perform the role of the core switching array. It will be shown that utilization of the diodes will retain the advantages of the core switch and will eliminate its disadvantages.The development of a combination sense and digit drive line free from the effects of noise and post-write disturb will also be presented.The design of an 8192 word 54 bit memory now under construction with a cycle time of less than 2 x 10-6 seconds will be discussed.","PeriodicalId":109454,"journal":{"name":"ACM '59","volume":"34 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1959-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ACM '59","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/612201.612256","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
In a linearly selected core configuration, the role of selection is removed from the memory core and an external system must be devised to select a desired line of cores. Several systems have been developed using a core switch array to drive the memory. This paper will describe a selection scheme utilizing diodes to perform the role of the core switching array. It will be shown that utilization of the diodes will retain the advantages of the core switch and will eliminate its disadvantages.The development of a combination sense and digit drive line free from the effects of noise and post-write disturb will also be presented.The design of an 8192 word 54 bit memory now under construction with a cycle time of less than 2 x 10-6 seconds will be discussed.