{"title":"hpFog: A FPGA-Based Fog Computing Platform","authors":"Tze Hon Tan, C. Y. Ooi, M. N. Marsono","doi":"10.1109/NAS.2017.8026862","DOIUrl":null,"url":null,"abstract":"This paper presents a versatile high performance FPGA-based Fog platform to accommodate the growth of Internet-of-Thing. Proposed platform allows hosted Fog applications to have high throughput computation while retaining required flexibility for post-deployment functional updates. Significantly, proposed platform has remote connectivity to allow customized circuitry of hosted applications to be software-defined by external management or development entity once deployed. Proposed platform occupied less than 14% of slices and 15% of BRAM logic resources in FPGA, which left more than 86% of slices and 85% of BRAM for application plane implementation.","PeriodicalId":222161,"journal":{"name":"2017 International Conference on Networking, Architecture, and Storage (NAS)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 International Conference on Networking, Architecture, and Storage (NAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NAS.2017.8026862","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9
Abstract
This paper presents a versatile high performance FPGA-based Fog platform to accommodate the growth of Internet-of-Thing. Proposed platform allows hosted Fog applications to have high throughput computation while retaining required flexibility for post-deployment functional updates. Significantly, proposed platform has remote connectivity to allow customized circuitry of hosted applications to be software-defined by external management or development entity once deployed. Proposed platform occupied less than 14% of slices and 15% of BRAM logic resources in FPGA, which left more than 86% of slices and 85% of BRAM for application plane implementation.