Memory-based multiprocessor translation-lookaside buffers: multiple paging arenas vs. large size TLB

Abstract

Translation-Lookaside B g e r s (TLBs) are virtual-address caches that are used to effrciently implement virtual memory. Teller, Kenner, and Snir 1161 proposed locating TLBs at memory. Using trace-driven simulations, Teller and Gottlieb 1151 compared the performance of memory-based TLBs with that of conventional processor-based TLBs. Their results indicate that memory-based TLBs can outperform processor-based TLBs in uniprogrammed multiprocessors, provided that memory is partitioned into equal-size clusters to which virtual-to-physical page mappings are fured (called paging arenas) and the number of paging arenas (M) increases with the number of processors (N). We extend Teller and Gottlieb's study by simulating multiprogrammed memory-based TLB systems with M = 2"', m=O, ..., 3 and larger-size TLBs. Our results agree with those of [I51 and indicate that for memory-based TLB systems, as M increases with N , performance improves, while the percentage of improvement &creases. We also show that comparable performance improvements can be attained by systems with one paging arena and larger memory-based TLBs. Unlike processor-based TLBs, the size of memory-based TLBs is not limited by processor chip size.