{"title":"Design and Performance Analysis of Digital Control Laws for Low Power High Frequency Switching Power Supply","authors":"S. K, V. S. Chakravarthi","doi":"10.1109/ICPEA.2019.8818516","DOIUrl":null,"url":null,"abstract":"This paper describes the design and performance analysis of the digital power supply regulator for System On Chip (SoC). The digital switching mode power supply consists of DC-DC buck converter providing 1V DC at 10 MHz switching frequency. To obtain a stable output under variable load and line conditions, three types of architectures for digital control lawsi.e. PID controller, Type III compensator and Sliding mode controller are explored. Simulation using Matlab/Simulink tool and Hardware-software co-simulation using Xilinx system generator is performed to analyze their performances. Among these three, Type III compensator is proposed which gives the best performance under wide load current and input voltage variations in terms of undershoot and response time. With type III compensator, a settling time in the range of 11-15 μs and maximum peak overshoot in the range of 2-8% is obtained for load variations and settling time in the range of 13-15μs and maximum peak overshoot in the range % of 2.2-4.5 % is obtained for line variations. A 13-bit DPWM which combines a 7-bit counter-comparator block with a 6 -bit second-order sigma-delta modulatoris designed to achieve high resolution and precise voltage regulation.","PeriodicalId":427328,"journal":{"name":"2019 IEEE 2nd International Conference on Power and Energy Applications (ICPEA)","volume":"214 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE 2nd International Conference on Power and Energy Applications (ICPEA)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICPEA.2019.8818516","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
This paper describes the design and performance analysis of the digital power supply regulator for System On Chip (SoC). The digital switching mode power supply consists of DC-DC buck converter providing 1V DC at 10 MHz switching frequency. To obtain a stable output under variable load and line conditions, three types of architectures for digital control lawsi.e. PID controller, Type III compensator and Sliding mode controller are explored. Simulation using Matlab/Simulink tool and Hardware-software co-simulation using Xilinx system generator is performed to analyze their performances. Among these three, Type III compensator is proposed which gives the best performance under wide load current and input voltage variations in terms of undershoot and response time. With type III compensator, a settling time in the range of 11-15 μs and maximum peak overshoot in the range of 2-8% is obtained for load variations and settling time in the range of 13-15μs and maximum peak overshoot in the range % of 2.2-4.5 % is obtained for line variations. A 13-bit DPWM which combines a 7-bit counter-comparator block with a 6 -bit second-order sigma-delta modulatoris designed to achieve high resolution and precise voltage regulation.