Built in self-test scheme for SRAM memories

Abstract

Due to the continuous miniaturization in the size and increase in the complexity of the SRAM circuit causes the SRAM memory more prone to failure due to variations in process parameters which significantly affect and acutely degrading the output of SRAM. To enhance the consistent performance and firmness of SRAM towards parametric failures, fault detection mechanism based on various different algorithms is used to call built in Self-Test. In this paper a different circuit is implemented for the detection of faults based on the transient condition during the write operation of SRAM cell which has the self in test ability. Effectiveness of developed Built in Self-Test circuit is presented in this paper. Simulations are performed against the introduced fault in 6T SRAM Cell. The cadence virtuoso tool is used to design the SRAM cell, differential amplifier level shifter and comparator circuit. All the circuit designed with 180nm technology.