Zeguo Yang, Ma Shang, Shuai Hu, Kun Zheng, Xuyuan Cao, Jienan Chen
{"title":"Design of FIR Filter Based on Algebraic Integer Quantization","authors":"Zeguo Yang, Ma Shang, Shuai Hu, Kun Zheng, Xuyuan Cao, Jienan Chen","doi":"10.1109/ICDSP.2018.8631667","DOIUrl":null,"url":null,"abstract":"Finite impulse response (FIR) digital filter is one of the key computational units in modern digital signal processing (DSP) systems. This paper presents a design method based on algebraic integer quantization for FIR digital filter with constant coefficients. To quantify the filter coefficients by appropriate algebraic integer, the multipliers can be replaced by the few adders, thereby reducing the implementation complexity. Compared with the traditional architectures, this method is faster and saves about 10%-20% in area. At the same time, this method has a better interconnection structure, which makes the area increment smaller when the timing constraints are strengthened.","PeriodicalId":218806,"journal":{"name":"2018 IEEE 23rd International Conference on Digital Signal Processing (DSP)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE 23rd International Conference on Digital Signal Processing (DSP)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICDSP.2018.8631667","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Finite impulse response (FIR) digital filter is one of the key computational units in modern digital signal processing (DSP) systems. This paper presents a design method based on algebraic integer quantization for FIR digital filter with constant coefficients. To quantify the filter coefficients by appropriate algebraic integer, the multipliers can be replaced by the few adders, thereby reducing the implementation complexity. Compared with the traditional architectures, this method is faster and saves about 10%-20% in area. At the same time, this method has a better interconnection structure, which makes the area increment smaller when the timing constraints are strengthened.