Interpolation-Based Multi-core Bounded Model Checking of HSTM Designs

Abstract

Bounded model checking, an effective way to reduce the state space, plays a significant role in verifying the reliability of a system. By combining bounded model checking and interpolation sequence, the verification of the properties out of some certain boundary can be completed. However, the introduction of interpolation-sequence increases the complexity of the model encoding and then affects the overall performance of a model checker. In order to alleviate the problem, we propose interpolation-based multi-core bounded model checking technology. Decomposing large problems into small ones, multicore parallel solutions can effectively shorten the elapsed time of problem processing. According to the conditional predicates, the paths in the model are divided into path clusters, and the interpolation sequence is used to determine if there is no counterexample path in each path cluster. Based on the nature of fixpoint in the path cluster, we propose a path cluster pruning algorithm in order to reduce the scale of the state space to be searched, which contributes to improving the efficiency. In this paper, we also present two optimization methods: incremental encoding and verification hypothesis. We have implemented the algorithms in the verification of the Hierarchical State Transition Matrix (HSTM) model design, and the experimental results have shown that our method have significantly increase the credibility of the verification results.