Area efficient and high throughput CAVLC encoder for 1920×1080@30p H.264/AVC

Abstract

This paper proposes a high performance hardware architecture design for the H.264/AVC CAVLC encoder. The proposed architecture can make a realtime process for 1920×1080 @ 30p. With the synthesis constraint of a 114MHz clock, the hardware cost of the proposed design is 7389 gates based on SS65LP 65nm technology.