Design of a 12-bit 0.83 MS/s SAR ADC for an IPMI SoC

Abstract

A 12-bit successive approximation register analog to digital converter (SAR ADC) built in an intelligent platform management interface (IPMI) system on chip (SoC) is proposed in this paper. The work is designed and fabricated in SMIC 0.13 μm CMOS process, using the fully differential C-R hybrid digital to analog converter (DAC) structure. Scaling capacitor is adopted to improve the precision and reduce the chip area. Through the optimization of placement and routing, the DAC achieves high precision. Besides, a multi-stage comparator is designed, and an offset calibration technique with capacitors is applied, too. The measurement results show that the effective number of bits (ENOB) of this ADC reaches 9.711 bit at Nyquist frequency with 0.83 MHz sampling frequency and the total current of the ADC is 970 μA with a 3.3 V power supply.