FPGA Implementation of Multiple Single Phase PWM Inverters with Configurable Duty Cycle and Dead Time

Abstract

Nowadays power inverters are widely used in various applications which range from domestic to industrial facilities. The Pulse Width Modulation (PWM) techniques are extensively used for the controlling of inverter circuit in which dead time, duty cycle, and frequency are important performance parameters. In the case of controlling multiple inverters with a single controller, control signals with embedded dead-time for all the inverters may lead to poor performance for some inverters due to shoot through and controlling of multiple inverters with common duty cycle and frequency cannot fulfill the requirement. Moreover, the use of an individual controller for each inverter is not cost-effective. In this work, the PWM switching strategies are designed with Verilog Hardware Description Language (HDL) and implemented using Xilinx Spartan-6 Nexys3 FPGA with precise control of dead time, duty cycle and frequency. This FPGA based controller enables us to control any inverter designed for a specific purpose and the same inverter for different applications by configuring its frequency and duty cycle. For the present work, we have generated six PWM signals with three different dead times and duty cycles which can control three single-phase PWM inverters with specified dead time and found that FPGA implementation provide desired output with negligible distortion avoiding shoot through.