{"title":"A 5/10/20/40 MHz 5th Order Active-RC Chebychev LPF for 802.11abg IF Receiver in 0.18 μm CMOS Technology","authors":"S. Delshadpour","doi":"10.1109/WAMICON.2019.8765462","DOIUrl":null,"url":null,"abstract":"A programmable 5/10/20/40 MHz BW active-RC filter in 0.18 um CMOS for a dual band 802.11 abg application is presented. This filter has a programmable high pass corner of 0.1/0.35/0.7 MHz and an in-band gain of 12dB. It is a Chebychev Thomas 1 implementation with low sensitivity to components variation with an integrated offset cancellation circuit that removes output offset of the mixer and filter together and sets the high pass corner. It drains 3.8/4.5/5.2/6.04mA for 5/10/20/40MHz BW from a 1.8V supply. The one-time frequency tuning during chip power up and BW adjustment is being done by a programmable capacitor bank.Each 5th order core has an area of 0.49 mm2 while two I & Q filters with RC tuning circuits have an area of 1.42 mm2.It has an IM3 of −41dBC, input referred noise of 18nV/sqrt(Hz) and output offset of 2mV.","PeriodicalId":328717,"journal":{"name":"2019 IEEE 20th Wireless and Microwave Technology Conference (WAMICON)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE 20th Wireless and Microwave Technology Conference (WAMICON)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/WAMICON.2019.8765462","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
A programmable 5/10/20/40 MHz BW active-RC filter in 0.18 um CMOS for a dual band 802.11 abg application is presented. This filter has a programmable high pass corner of 0.1/0.35/0.7 MHz and an in-band gain of 12dB. It is a Chebychev Thomas 1 implementation with low sensitivity to components variation with an integrated offset cancellation circuit that removes output offset of the mixer and filter together and sets the high pass corner. It drains 3.8/4.5/5.2/6.04mA for 5/10/20/40MHz BW from a 1.8V supply. The one-time frequency tuning during chip power up and BW adjustment is being done by a programmable capacitor bank.Each 5th order core has an area of 0.49 mm2 while two I & Q filters with RC tuning circuits have an area of 1.42 mm2.It has an IM3 of −41dBC, input referred noise of 18nV/sqrt(Hz) and output offset of 2mV.