A reusable embedded DRAM macrocell

Abstract

A charged based analysis is used to compare three DRAM cells embedded in a 0.25 /spl mu/m ASIC environment. Critical charge, bit-line response, and sense amplifier sensitivity are calculated. Wafer probe measurements are shown that demonstrate milli-second hold times and explanations presented in support of using multi-transistor DRAM cells for the vast majority of high performance embedded ASIC applications.