A 60GHz variable-gain LNA in 65nm CMOS

A. Natarajan, S. Nicolson, Ming-Da Tsai, B. Floyd
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引用次数: 31

Abstract

A four-stage 60 GHz low-noise amplifier is implemented in 65 nm CMOS with nMOS ft of 210 GHz. The LNA incorporates a reflection-type attenuator to provide variable gain with improved linearity in low-gain mode and a tunable notch filter for image rejection. The LNA, which consists of two common-source stages followed by two cascode stages, consumes 30.8 mW and achieves 5.9 dB NF and 15 dB gain at 60 GHz. The variable attenuator provides 10 dB of gain variation with the input-referred 1 dB compression point of the LNA being -15.1 dBm in high gain mode and -6 dBm in the low-gain mode. Each tunable notch filter stage provides an additional 8 dB attenuation of 37 GHz image signals, with the four-stage LNA achieving more than 35 dB image-rejection.
65nm CMOS中的60GHz可变增益LNA
在65nm CMOS中实现了一个四级60ghz低噪声放大器,nMOS ft为210 GHz。LNA集成了一个反射型衰减器,在低增益模式下提供可变增益和改进的线性度,以及一个可调陷波滤波器用于图像抑制。LNA由两个共源级和两个级联码级组成,功耗30.8 mW,在60 GHz时可实现5.9 dB的NF和15 dB的增益。可变衰减器提供10db的增益变化,LNA的输入参考1db压缩点在高增益模式下为-15.1 dBm,在低增益模式下为-6 dBm。每个可调陷波滤波器级可对37 GHz图像信号提供额外的8 dB衰减,四级LNA可实现35 dB以上的图像抑制。
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