M. Maiore, G. Berretta, G. Conti, E. Pirrone, C. Campisi
{"title":"A 63 % PAE and 10:1 VSWR at 3.3 V power amplifier in 0.25 /spl mu/m SiGe BiCMOS for DCS and PCS applications","authors":"M. Maiore, G. Berretta, G. Conti, E. Pirrone, C. Campisi","doi":"10.1109/RWS.2006.1615141","DOIUrl":null,"url":null,"abstract":"A fully integrated monolithic power amplifier (PA) for DCS/PCS applications has been integrated in 0.25 /spl mu/m SiGe BiCMOS technology. The three-stages power amplifier delivers 31.8 dBm of output power (Pout) with 63% power added efficiency (PAE). A 100 /spl Omega/ differential input impedance power amplifier module (PAM) has been designed to validate the proposed circuit. The PA includes an on chip temperature compensated bias block. The bulky and expensive RF chokes normally used for the first and second stage have been integrated on-chip, in order to minimize the number of passive components into the module. The reported PA is planned to be used in an envelope elimination and restoration (EER) architecture with 3.3 V supply voltage. Furthermore, the PA can withstand up to 10:1 load voltage standing wave ratio (VSWR) at no permanent damage.","PeriodicalId":244560,"journal":{"name":"2006 IEEE Radio and Wireless Symposium","volume":"3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 IEEE Radio and Wireless Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RWS.2006.1615141","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 4
Abstract
A fully integrated monolithic power amplifier (PA) for DCS/PCS applications has been integrated in 0.25 /spl mu/m SiGe BiCMOS technology. The three-stages power amplifier delivers 31.8 dBm of output power (Pout) with 63% power added efficiency (PAE). A 100 /spl Omega/ differential input impedance power amplifier module (PAM) has been designed to validate the proposed circuit. The PA includes an on chip temperature compensated bias block. The bulky and expensive RF chokes normally used for the first and second stage have been integrated on-chip, in order to minimize the number of passive components into the module. The reported PA is planned to be used in an envelope elimination and restoration (EER) architecture with 3.3 V supply voltage. Furthermore, the PA can withstand up to 10:1 load voltage standing wave ratio (VSWR) at no permanent damage.