A 63 % PAE and 10:1 VSWR at 3.3 V power amplifier in 0.25 /spl mu/m SiGe BiCMOS for DCS and PCS applications

M. Maiore, G. Berretta, G. Conti, E. Pirrone, C. Campisi
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引用次数: 4

Abstract

A fully integrated monolithic power amplifier (PA) for DCS/PCS applications has been integrated in 0.25 /spl mu/m SiGe BiCMOS technology. The three-stages power amplifier delivers 31.8 dBm of output power (Pout) with 63% power added efficiency (PAE). A 100 /spl Omega/ differential input impedance power amplifier module (PAM) has been designed to validate the proposed circuit. The PA includes an on chip temperature compensated bias block. The bulky and expensive RF chokes normally used for the first and second stage have been integrated on-chip, in order to minimize the number of passive components into the module. The reported PA is planned to be used in an envelope elimination and restoration (EER) architecture with 3.3 V supply voltage. Furthermore, the PA can withstand up to 10:1 load voltage standing wave ratio (VSWR) at no permanent damage.
在0.25 /spl mu/m SiGe BiCMOS中,用于DCS和pc应用的63% PAE和10:1 VSWR 3.3 V功率放大器
一款用于DCS/PCS应用的全集成单片功率放大器(PA)已集成在0.25 /spl mu/m SiGe BiCMOS技术中。三级功率放大器提供31.8 dBm输出功率(Pout),功率附加效率(PAE)为63%。设计了一个100 /spl ω /差分输入阻抗功率放大器模块(PAM)来验证所提出的电路。该放大器包括片上温度补偿偏置块。通常用于第一级和第二级的笨重且昂贵的射频扼流圈已集成在芯片上,以尽量减少模块中无源元件的数量。所报道的PA计划用于3.3 V供电电压的包络消除和恢复(EER)架构。此外,PA可以承受高达10:1的负载电压驻波比(VSWR)而不会永久损坏。
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