Design and Physical Implementation of a Low Frequency On-Chip Oscillator

Jaydeep Banik Mazumdar, K. Sarawadekar
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引用次数: 1

Abstract

In this paper, a square wave with 10 kHz frequency is designed to be used as an on-chip oscillator for a Wireless Sensor Node System On Chip (WSN-SOC). The proposed circuit generates high-frequency oscillations without the need for any external crystal oscillator using a ring oscillator. An asynchronous counter is used as a frequency divider circuit to decrease the frequency of the oscillations to the desired frequency. A buffer at the output stage increases the net current so that the oscillator can drive multiple loads. The circuit is designed as per the full custom ASIC flow in the 180 nm technology library provided by the foundry - Semi-Conductor Laboratory, India. The schematic and the layout are done on the Cadence Virtuoso tool. Physical verification is performed using Mentor Graphics Calibre tool. Post-layout simulation is done using Synopsys HSpice tool. The post-layout simulations of the oscillator occupying an area of about 223um x 118 um, show a square wave with a frequency of 10.59 kHz, very close to the desired frequency, consuming 9.408 uW average power at 1.8 V supply.
一种低频片上振荡器的设计与物理实现
本文设计了一种频率为10khz的方波作为片上振荡器,用于无线传感器节点片上系统(WSN-SOC)。所提出的电路产生高频振荡,而不需要使用环形振荡器的任何外部晶体振荡器。异步计数器用作分频电路,将振荡的频率降低到所需的频率。输出级的缓冲器增加净电流,使振荡器可以驱动多个负载。该电路是根据印度半导体实验室提供的180纳米技术库中的完整定制ASIC流程设计的。原理图和布局是在Cadence Virtuoso工具上完成的。使用Mentor Graphics Calibre工具进行物理验证。布局后仿真使用Synopsys HSpice工具完成。该振荡器的布局后仿真面积约为223um x 118um,显示出频率为10.59 kHz的方波,非常接近期望频率,在1.8 V电源下消耗9.408 uW的平均功率。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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