Architecture Design for the Context Formatter in the H.264/AVC Encoder

Abstract

Hardware accelerators for H.264/AVC using arithmetic coding require special approaches to achieve high throughputs. This paper proposes an efficient architecture for the context formatter that is a part of the H.264/AVC binary encoder. Five versions of the architecture are developed to match different throughputs. The implementation results show that the proposed versions of the context formatter match the performance of corresponding arithmetic coders