A 14mW 2.5MS/s 14bit Sigma-Delta Modulator Using Pseudo-Differential Split-Path Cascode Amplifiers

IEEE Custom Integrated Circuits Conference 2006 Pub Date : 2006-09-01 DOI:10.1109/CICC.2006.320961

Z. Cao, Tongyu Song, Shouli Yan

引用次数: 6

Abstract

Switched-capacitor biased pseudo-differential split-path cascode amplifiers are proposed to achieve high power efficiency and small die area for a 14-bit 2.5MS/s DeltaSigma modulator. Sufficient power supply rejection is maintained through the biasing circuit. A novel signal and reference sampling network eliminates input common-mode voltages and relaxes op-amp linearity requirements, making it possible to use short channel length transistors for speed and power efficiency. A prototype chip is fabricated in a 0.25mum CMOS technology with a core area of 0.27mm2. Experimental results show that 84dB dynamic range is achieved with the 1.25MHz signal bandwidth when clocked at 120MHz. The power dissipation is 14mW at 2.5V including the on-chip voltage reference buffers

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基于伪差分分路级联码放大器的14mW 2.5MS/s 14bit Sigma-Delta调制器

为了实现14位2.5MS/s DeltaSigma调制器的高功率效率和小芯片面积，提出了一种开关电容偏置伪差分分路级联放大器。通过偏置电路保持足够的电源抑制。一种新颖的信号和参考采样网络消除了输入共模电压并放宽了运算放大器的线性度要求，从而可以使用短通道长度的晶体管来提高速度和功率效率。原型芯片采用0.25 μ m CMOS技术制造，核心面积为0.27mm2。实验结果表明，当时钟频率为120MHz时，信号带宽为1.25MHz，动态范围可达84dB。包括片上参考电压缓冲器在内，2.5V时的功耗为14mW

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

IEEE Custom Integrated Circuits Conference 2006

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