Comparisons of implant-through-contact and conventional high-voltage TFTs

Abstract

An implant-through-contact (ITC) scheme to fabricate offset-gate high-voltage (HV) thin-film transistors (TFTs) has recently been proposed. The ITC scheme saves the n/sup +/ mask required in the conventional methods by performing the n/sup +/ source-drain implant only after contact opening. The device performances of ITC and conventional HV transistors has been fully characterized and compared. Both ITC and conventional HV TFTs have been fabricated on the same wafers by making the ITC TFTs during the conventional n/sup +/ source-drain implant and applying another n/sup +/ implant after contact opening for forming their source-drain. Experimental results show that ITC transistors have a higher breakdown voltage. ITC transistors also show better alignment tolerance in regard to the drain offset length, which is beneficial for large area applications. The observed improvements are ascribed to the existence of a drain metal field plate overlapping the offset region of ITC TFTs. The drain metal pad serves to accumulate and enhance carriers along the offset region, thus minimizing its sensitivity to the length. This has been confirmed by fabricating conventional HV TFTs with and without the drain overlapping field plate.<>