Fabrication and Dielectric Breakdown of 3C-SiC/SiO2 MOS Capacitors

Abstract

MOS capacitors with thick (≈65nm) SiO2 gate oxide were fabricated on 3C-SiC/Si substrates and characterised (CV and IV) at room temperature to study the state of the art 3C-SiC/SiO2 interface. A low interface trap density of ~2.5×1011cm−2eV−1was obtained on N2O annealed devices using the high-low method. Gate oxide was biased with elevated voltage and the distribution of cumulative failed devices was studied. Two failure mechanisms were identified with mechanism 1 dominating the 6-8.5MV/cm range, and mechanism 2 becoming more obvious above S.5MV/cm. The failure rate of fabricated MOS capacitors with a diameter of 100µm at 3MV/cm and room temperature was estimated to be ~3450 PPM.