FPGA Hardware Implementation of the Yolo Subclass Convolutional Neural Network Model in Computer Vision Systems

Abstract

The computing unit (CU) of the computer vision system (CVS) has been developed based on a system on a chip (SOC) with the Xilinx Field-Programmable Gate Array (FPGA). A new model of a convolutional neural network (CNN) tiny-YOLO-Inception-ResNet2 related to neural networks of the YOLO subclass was proposed. A feature of this model is the presence of two Inception-ResNet modules. The weight coefficients of the trained software-implemented CNN of the same model were used. Images from the Pascal VOC 2007 dataset were used to train and test these CNN models. The research of the CU effectiveness was carried out. Firstly, we study the detection time of one image which spent in each layer of the CNN model and of the whole model depending on the number of universal computing units in the CU. Also, the study of the detecting objects accuracy depending on the bit depth (16 or 32 bits) of floating-point numbers was carried out. It is concluded that it is necessary to perform calculations using 32-bit floating-point numbers. It is shown that the power consumption of the CU did not exceed 12 Watts during all experiments.