Zhenhuan Zhan, Wei Hao, Yan Tian, Da-wei Yao, Xianhong Wang
{"title":"A Design of Versatile Image Processing Platform Based on the Dual Multi-core DSP and FPGA","authors":"Zhenhuan Zhan, Wei Hao, Yan Tian, Da-wei Yao, Xianhong Wang","doi":"10.1109/ISCID.2012.210","DOIUrl":null,"url":null,"abstract":"As an application of TI's latest multi-core DSP chip TMS320C6678 and Xilinx's FPGA chip XC5VLX110T, This paper designed and implemented a dual-DSP and FPGA real-time image processing system based on the Serial Rapid IO (SRIO), Hyperlink and reconfigurable technology. It used TMS320C6678 on-chip SRIO and Hyperlink interface module, XC5VLX110T on-chip Rocket IO modules, reconfigurable technology to implement a DSP and FPGA loosely coupled parallel interconnection reconfigurable system. on Embedded operating system's DSP / BIOS architecture, this paper implemented the program of hardware driver of bottom layer and the corresponding data transfer procedures, and also completed the transmission of digital images.","PeriodicalId":246432,"journal":{"name":"2012 Fifth International Symposium on Computational Intelligence and Design","volume":"27 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 Fifth International Symposium on Computational Intelligence and Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISCID.2012.210","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 11
Abstract
As an application of TI's latest multi-core DSP chip TMS320C6678 and Xilinx's FPGA chip XC5VLX110T, This paper designed and implemented a dual-DSP and FPGA real-time image processing system based on the Serial Rapid IO (SRIO), Hyperlink and reconfigurable technology. It used TMS320C6678 on-chip SRIO and Hyperlink interface module, XC5VLX110T on-chip Rocket IO modules, reconfigurable technology to implement a DSP and FPGA loosely coupled parallel interconnection reconfigurable system. on Embedded operating system's DSP / BIOS architecture, this paper implemented the program of hardware driver of bottom layer and the corresponding data transfer procedures, and also completed the transmission of digital images.