High Speed FFT Processor Implementation

Abstract

This paper describes recent progress in the implementation of a high speed Fast Fourier Transform (FFT) processor with state-of-the-art VLSI circuits. Initial efforts have produced FFT and inverse FFT processors that operate at data rates of up to 40 MHz (complex). The current implementation computes transforms of up to 16,384 points in length by means of the McClellan and Purdy radix 4 pipeline FFT algorithm. The arithmetic is performed by single chip 22 bit floating point adders and multipliers, while the interstage reordering is performed by delay commutators implemented with semi-custom VLSI. This paper explains the pipeline FFT implementation and focuses attention on our current activity which involves developing a fixed point arithmetic version using CMOS multipliers and adders to reduce the power consumption.