RISC-V Core with Approximate Multiplier for Error-Tolerant Applications

Abstract

RISC-V is an open-source instruction set architecture with customizable extensions to introduce operations like multiplication, division, atomic functions, and floating-point operations. In this paper, a new approximate multiplier is integrated with RI5CY (CV32E40P) processor, which can perform integer and floating-point multiplication for error-tolerant applications. The multiplication operation is required in various engineering and scientific applications, including image processing, digital signal processing, and many others. The proposed approximate multiplier is based on linear CORDIC (COordinate Rotation Digital Computer) algorithm and implemented by using only shift-add operations. It can perform multiplication and MAC (Multiply and accumulate) operations. The FPGA (Field programmable gate arrays) implementation results and ASIC (Application-specific integrated circuit) synthesis results for the proposed approximate multiplier along with RI5CY core are reported. The proposed design with RI5CY core is implemented on FPGA Xilinx Zedboard, which improves the performance by 20% and reduces power delay product (PDP) by 15.79% over the existing multipliers of the RI5CY core. Moreover, RI5CY core with the proposed approximate multiplier is synthesized using Industrial 130 nm standard cell library (ISCL) and Sub-threshold 130 nm standard cell library (STSCL) in Synopsys DC compiler. In the case of STSCL, RI5CY core with proposed approximate multiplier has 11.76% less power-consumption, 27.27% less delay, and 38.77% PDP compared to the existing multipliers of the RI5CY core.