Low power 32-bit UniRISC with Power Block Manager

Abstract

In this paper we propose a low power technique named Power Block Manager (PBM) to reduce power consumption in various function units within a microprocessor. Power Block Manager considers each function block as an independent object. To disable running those function units which neither work nor affect the output results, the system can save the dynamic power dissipation. The PBM architecture involves three parts. The instruction type detector classifies the instructions. The power block table points out which power blocks can be turned on or off according to the instruction type. The scheduler arranges the power control signals to meet the pipelined system. We apply the PBM system to a 32-bit microprocessor named UniRISC which is designed by CCU SoC Center, and take three applications to examine the power. After the Post-Layout experiment, the processor with PBM system can save 20.1~30.2% power consumption.