Characterizing Anomalies of a Multicore ARMv7 Cluster with Parallel N-Body Simulations

Abstract

ARM processors are beginning to gain attention from the HPC community due to its performance and energy efficiency characteristics. When developing HPC applications for such test beds developers assume that the computation resources available are homogeneous. However, we observed some anomalies when executing a relatively simple HPC application (an NBody simulation). One of the cores in all available nodes presented some variabilities in the computation time. This unexpected behavior was not observed on the second core of each node. In this paper, we aim at characterizing such anomalies, seen in a multicore ARMv7 8-node cluster. We also attempted to isolate and remove all possible interferences that could be contributing to this unexpected behavior, including compilation directives, dynamic processor frequency scaling and communication. Results show that such anomaly might be correlated with the architecture of the dual-core chip. We also analyze the effects of different deployments of MPI process in the total execution time and correlate them to the application and the test bed.