An investigation into the implementation costs of residue and high radix arithmetic

Abstract

Due to the need for coexistence with binary logic, the implementation of multiple-valued logic must deal with the representations that are conceptually multiple-valued, but physically binary. Some theoretical insights about the VLSI implementation based on a programmable logic array (PLA) approach are presented. The study of these output functions reveals an interesting problem domain that parallels the number theory. It is found that the binary-related radices are not just efficient or direct-packing, but also lower in terms of silicon costs. Implementation of the individual modulo adders and multipliers that form the core for designing a residual number arithmetic unit is discussed. The costs involved in developing these subsystems can then be directly related to the design of the overall system. This tutorial demonstrates that the power-of-two advantage in the implementation costs may be technology-independent.<>