Comparison of the Motorola DSP56000 and the Texas Instruments TMS320C25 digital signal processors for implementing a four error correcting (127,99) BCH error control code decoder

Conference Proceeding IEEE Pacific Rim Conference on Communications, Computers and Signal Processing Pub Date : 1989-06-01 DOI:10.1109/PACRIM.1989.48373

W. Weeks, W. Little, V. Bhargava, T. Gulliver

{"title":"Comparison of the Motorola DSP56000 and the Texas Instruments TMS320C25 digital signal processors for implementing a four error correcting (127,99) BCH error control code decoder","authors":"W. Weeks, W. Little, V. Bhargava, T. Gulliver","doi":"10.1109/PACRIM.1989.48373","DOIUrl":null,"url":null,"abstract":"The Motorola DSP56000 and the Texas Instruments TMS320C25 digital signal processors are compared on the basis of their use in implementing a four error correcting (127,99) BCH code decoder. The code is being used as a basis for comparing various decoder implementations. Algorithms for efficient microprocessor implementations of a decoder are presented. The ability to implement time-critical steps in these algorithms is the basis for comparing the DSP56000 and the TMS320C25. The DSP56000's comparatively general-purpose architecture and certain unique features provide a higher bit rate decoder than can be implemented on the TMS320C25. Assembly language programs have been written and tested for performance and timing using IBM PC-based simulators of the processors. A complete decoder has been implemented on the DSP56000, achieving an average bit rate in excess of 1 million b/s.<<ETX>>","PeriodicalId":256287,"journal":{"name":"Conference Proceeding IEEE Pacific Rim Conference on Communications, Computers and Signal Processing","volume":"81 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Conference Proceeding IEEE Pacific Rim Conference on Communications, Computers and Signal Processing","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/PACRIM.1989.48373","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 5

Abstract

The Motorola DSP56000 and the Texas Instruments TMS320C25 digital signal processors are compared on the basis of their use in implementing a four error correcting (127,99) BCH code decoder. The code is being used as a basis for comparing various decoder implementations. Algorithms for efficient microprocessor implementations of a decoder are presented. The ability to implement time-critical steps in these algorithms is the basis for comparing the DSP56000 and the TMS320C25. The DSP56000's comparatively general-purpose architecture and certain unique features provide a higher bit rate decoder than can be implemented on the TMS320C25. Assembly language programs have been written and tested for performance and timing using IBM PC-based simulators of the processors. A complete decoder has been implemented on the DSP56000, achieving an average bit rate in excess of 1 million b/s.<>

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摩托罗拉DSP56000和德州仪器TMS320C25数字信号处理器实现四纠错(127,99)BCH错控码解码器的比较

对摩托罗拉DSP56000和德州仪器TMS320C25数字信号处理器在实现四纠错(127,99)BCH码解码器中的应用进行了比较。该代码被用作比较各种解码器实现的基础。提出了解码器的高效微处理器实现算法。在这些算法中实现时间关键步骤的能力是比较DSP56000和TMS320C25的基础。DSP56000相对通用的架构和某些独特的功能提供了比TMS320C25更高的比特率解码器。使用基于IBM pc的处理器模拟器编写和测试了汇编语言程序的性能和时序。在DSP56000上实现了一个完整的解码器，实现了超过100万b/s的平均比特率

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Conference Proceeding IEEE Pacific Rim Conference on Communications, Computers and Signal Processing

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