Variation tolerance and error resilience in a low power wireless receiver

Abstract

Power consumption of digital baseband processing of a wireless receiver can be reduced by operating the circuits at a reduced voltage where setup timing errors occur occasionally in a controlled way. One of the challenges is then to estimate the BER of the receiver and to create a control loop that controls the voltage such that the estimated BER is within the specifications of the system. The paper describes two mechanisms to realize such a control loop. The first one uses parity-based error detection; the second one is based on the application of forward error correction in the system. Both mechanisms have been modeled in an industrial low power receiver design that includes a model for setup timing error injection. Simulation results show that the control loops are able to accurately control the voltage to the lowest possible level such that the BER stays within the specified constraints.