22-nm FDSOI CMOS Noise Modeling and Analysis in mm-Wave Frequency Range

Abstract

This paper presents the modeling and analysis of the high-frequency noise in 22-nm FDSOI CMOS technology. Experimental noise parameters up to 170 GHz of a multi-finger n-channel transistor are extracted by utilizing the tuner-based method. The Pucel (PRC) noise model is applied and validated for prediction of 22-nm FDSOI noise characteristics from low frequencies to D-band frequencies. In addition, extraction and analysis of the model parameters versus drain current at the W-band frequency 94 GHz are demonstrated.