Reliability Aspects of Memristive Devices for Computation-in-Memory Applications

Abstract

Due to the high amount of data being processed in modern computing systems, the conventional physical separation of data processing and data storage limits the computing performance. Thus, new computing paradigms such as computation-in-memory are investigated to alleviate the limitations of the conventional computing scheme. Memristive devices based on the valence change mechanism offer multilevel programming capability in the CMOS compatible voltage range at reasonable speed. These properties are exploited for different computation-in-memory approaches such as Boolean logic, vector-matrix multiplications or arithmetic operations. One obstacle is the reliability of these devices. They typically show switching variability from device-to-device and cycle-to-cycle as well as read instability in the high resistive state. Here, we discuss the basic reliability issues of valence change memory cells and show a variability-aware compact model. Further, the influence of these reliability aspects on vector-matrix multiplications is discussed.