Investigations on device design parameters of all-oxide transparent charge-trap memory thin-film transistors

Abstract

Charge-trap memory thin film transistors employing In-Ga-Zn-O thin films as active channel and charge-trap layers (CTLs) were fabricated and characterized. To optimize process conditions, the design parameters were categorized into two parts. First, the thickness effects of double-layered tunneling oxide were examined and the 5 nm/5 nm configuration was chosen for guaranteeing process window and device performance. Secondly, the CTL thickness effects were investigated and the device using 30 nm-thick CTL showed most desirable behaviors including superior memory operation and device uniformity. The CTL geometry was also found to have significant impact on nonvolatile memory operations.