Test generation for gate level sequential machines: algorithms and implementation issues

Abstract

Algorithms and implementation issues concerning a Boolean factorization based test generation package for gate level sequential machines are discussed. Practical aspects like justification and propagation weights computation and targeted test pattern generation are treated in depth, giving both theoretical and pseudo-code solutions. The experimental results showed that the proposed method was effective in generating sufficiently high fault coverage for the standard set of ISCAS'89 benchmark synchronous sequential circuits.<>