Sub-10-µm Coil Design for Multi-Hop Inductive Coupling Interface

Abstract

Sub-10-µm on-chip coils are designed and prototyped for the multihop inductive coupling interface in a 40-nm CMOS. Multi-layer coils and a new receiver circuit are employed to compensate the decrease of the coupling coefficient due to the small coil size. The prototype emulates a 3D stacked module with 8 dies in a 7-nm CMOS and shows that a 0.1-pJ/bit and 41-Tb/s/mm2 inductive coupling interface is achievable.