Parallel computation of neural networks in a processor pipeline with partially shared memory

Abstract

A novel parallel architecture of a processor pipeline is proposed, comprising linearly connected processors via dual bank switchable memory blocks. A layered neural network with the back-propagating error algorithm is adopted as a benchmark test. The essential part of the algorithm is a matrix multiplication with a vector. An experimental system was implemented, and several measurements were made which demonstrate the suitability of the proposed architecture in some practical applications.<>