Stochastic wire-length model with TSV placement on periphery area

Abstract

Despite of numerous advantages of three dimensional integrated circuits (3D-ICs), their commercial success remains limited. The reason lies, in part, on the lack of physical design tools about Through-Silicon-Vias (TSVs) and 3D die stacking. In this paper, we propose a novel TSV placement method on the periphery of the dies. Based on this method, we derive a novel mathematical model to estimate 3D-IC wire-length and area with TSVs before floor-planning. We analyze the impact of TSVs on silicon area and wire-length. A case study with ISCAS benchmark circuits demonstrates that the proposed TSV placement method reduces the chip area and alleviates the reliability issues.