Membership test logic for delay-insensitive codes

Abstract

Delay-insensitive (unordered) codes have been used to encode data in various asynchronous systems such as asynchronous circuits and buses. In this paper, a new general approach to designing completion-detection circuits (completion checkers) for asynchronous circuits and systems using delay-insensitive codes is presented. It is shown that a completion-detection circuit for many delay-insensitive codes can be easily and efficiently built in a systematic way by using multi-output threshold circuits. The results presented here remain in a sharp contrast with the conclusions reached by Akella et al. (1996) where similar designs-called enumeration-based decoders-were found impractical due to excessive complexity.