Accelerated Edge Detection Algorithm for High-Speed Applications

Abstract

Digital Image Processing (DIP) is a growing field for various applications, such as autonomous vehicles and video surveillance. To improve the performance of DIP systems, image processing algorithms are implemented in hardware rather than software. The idea here is primarily to get a faster system than software imaging or other alternative hardware. Field-programmable gate arrays (FPGAs) have the advantages of parallel processing, low cost, and low power consumption. These semiconductor devices contain many logic blocks that can be programmed to perform everything from basic digital gate-level technology to complex image processing algorithms. This paper provides an enhancement pipeline system architecture using AXI interface to implement image processing algorithms such as Sobel edge detection and mean filters on the Zybo z7 Zynq 7010 board using Verilog HDL language. The system is implemented in a 512×512 image that takes 0.009ms in the processing system.