A configuration-speed acceleration method for a sequential circuit using a negative logic implementation

Abstract

An optically reconfigurable gate array (ORGA) was developed recently as one multi-context device to achieve high-speed reconfiguration. Since quick context switching allows implementation of many functions onto a gate array without idle time, fast reconfiguration is extremely important for multi-context devices. In ORGAs, the easiest way to increase the reconfiguration frequency is to use high-power lasers, but such lasers increase the ORGA power consumption and package size. In some cases, they might even require a cooling system. For that reason, this paper presents a configuration speed acceleration method for a sequential circuit using a negative logic implementation without ORGA architecture modification and without any increase of laser power. Based on experimentally obtained results, this paper clarifies the acceleration method's effectiveness.