{"title":"Sensitivity analysis of transformerless PV inverter topologies to physical variations of power devices","authors":"A. Pigazo, Holger Jedtberg, Marco Liserre","doi":"10.1109/IECON.2014.7048813","DOIUrl":null,"url":null,"abstract":"Transformerless (TL) topologies are employed in 1φ PV inverter topologies due to their small size and low weight. Avoiding the grid side transformer requires the modulation technique and the basis topology to be accordingly changed in order to mitigate dc current components in the grid side and the leakage current to ground. This paper carries out a sensitivity analysis of selected TL topologies. This analysis investigates the impact of parameter variations of the employed semiconductor devices and detects the device which affects the most the overall efficiency. As a result, relevant info for engineers selecting the most suitable power devices for the implementation of a certain TL topology is provided.","PeriodicalId":228897,"journal":{"name":"IECON 2014 - 40th Annual Conference of the IEEE Industrial Electronics Society","volume":"55 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IECON 2014 - 40th Annual Conference of the IEEE Industrial Electronics Society","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IECON.2014.7048813","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
Transformerless (TL) topologies are employed in 1φ PV inverter topologies due to their small size and low weight. Avoiding the grid side transformer requires the modulation technique and the basis topology to be accordingly changed in order to mitigate dc current components in the grid side and the leakage current to ground. This paper carries out a sensitivity analysis of selected TL topologies. This analysis investigates the impact of parameter variations of the employed semiconductor devices and detects the device which affects the most the overall efficiency. As a result, relevant info for engineers selecting the most suitable power devices for the implementation of a certain TL topology is provided.