Implementation of a parameterizable sorting network for spatial modulation detection on FPGA

Abstract

In this paper, implementation results of a bitonic-merge sorting network are presented. This is used on a detection algorithm for MIMO Spatial Modulation (SM) communications and it is implemented on an Intel Altera Cyclone IV FPGA. This sorting network has the added peculiarity that it indicates the index or entrance order of the numbers to sort; i.e., each element of the sorted vector has a certain amount of bits concatenated indicative of their original position. Also, as it is completely combinational, the amount of time taken to sort is only the inherent propagation delay, having great performance even if it is not suitable to sort a great quantity of elements. It is possible to implement an entirely parametric sorting network in terms of the number of elements to sort and the bits used for representation of these elements, and the use of resources for index representation is comparable to present implementations.