Area Efficient Memory-Based Even-Multiple-Storage Multiplier for Higher Input

Abstract

VLSI architecture design of DSP focuses on designtechniques for the realization of a dedicated Very Large Scale Integrated (VLSI) systems for signal processing, image processing, and other communication applications. The VLSI design techniques and systolic architectures will be used for exploring the speed-area-power tradeoffs for different DSP applications. Memory-based structures are a pertinent and fitting choice for a large number of signal processing implementations that implicate multiplication with a certain set of coefficients. In this paper, however, we show a memory-based approach that can be advantageous for reduced-latency and area reducing implementations in which memory processing time is shorter than the normal computation-time effectuated in traditional multipliers. The key factor of our paper is lookup table (LUT) optimization which reduces the area and power, also a pipelined version of the memory-based multiplier reduces the combinational path delay.